1. Field of the Invention
The present invention relates generally to the field of electrical devices. More particularly, the present invention relates to the field of phase-locked loops.
2. Description of the Related Art:
For the synchronous transmission of digital data for typical systems, a transmitting unit transmits a data signal at a constant rate as determined by a clock local to the transmitting unit, and a receiving unit attempts to receive the data signal at the same constant rate. The transmitting unit may transmit the data signal without a clock signal as the system then requires only approximately one-half of the bandwidth necessary for the transmission of a data signal with a clock signal. To receive transmitted data signals with minimized errors, then, the receiving unit attempts to recover the clock signal associated with the data signal.
To recover the clock signal, the receiving unit may use a phase-locked loop (PLL) clock recovery system that includes a phase detector and a voltage controlled oscillator (VCO) that controls the frequency of the clock local to the receiving unit. The phase detector detects the phase difference between the received data signal and the clock local to the receiving unit (i.e., phase error), and then modulates the frequency of this local clock to bring the local clock into approximately the same phase and frequency as the received data signal.
To modulate the frequency of the local clock, a typical phase detector generates and outputs a pump-up pulse on a pump-up node and a pump-down pulse on a pump-down node. The frequency of the local clock is increased by a pump-up pulse and is decreased by a pump-down pulse. The signal on the pump-down node is subtracted from the signal on the pump-up node to produce a difference signal. This difference signal is integrated by an integrator, and the resulting integrated signal may be used as a control signal for the voltage controlled oscillator (VCO) to control the frequency of the local clock. In this manner, the receiving unit synchronizes its local clock to minimize errors in receiving transmitted data.